1. Field of the Invention
The present invention relates to silicon nano wires, a semiconductor device including the same, and a method of manufacturing the silicon nano wires.
More particularly, the present invention relates to nano wires having a p-n junction structure in which the size and distribution of nucleation regions for forming the nano wires are accurately controlled when forming silicon nano wires, and a method of manufacturing the same.
2. Description of the Related Art
Nano wires are currently being widely researched, and are a next-generation technology used in various devices such as optical devices, transistors, and memory devices. Materials used in conventional nano wires include silicon, zinc oxide, and gallium nitride, which is a light emitting semiconductor. The conventional nano wire manufacturing technique is sufficiently developed to be used for altering of the length and width of nano wires.
Quantum dots or nano light emitting devices using quantum dots are used in conventional nano light emitting devices. Organic electroluminescent (EL) devices using quantum dots have high radiative recombination efficiency but low carrier injection efficiency. Gallium nitride light-emitting diodes (GaN LEDs), which use quantum wells, have relatively high radiative recombination efficiency and carrier injection efficiency. However, it is very difficult to mass produce GaN LED due to a defect caused by the difference in the crystallization structures of the GaN LED and a commonly used sapphire substrate. Thus the manufacturing costs of GaN LEDs are relatively high. A nano light emitting device using nano wires has very high radiative recombination efficiency and relatively high carrier injection efficiency. In addition, the manufacturing process of a nano light emitting device is simpler and a nano light emitting device can be formed to have a crystallization structure that is practically similar to that of a substrate. Thus it is easier to mass produce the nano light emitting device.
FIGS. 1A through 1D are cross-sectional views illustrating a vapor-liquid-solid (VLS) method, which is a conventional method of manufacturing nano wires.
Referring to FIG. 1A, first, a substrate 11 is provided. The substrate 11 is a commonly used silicon substrate.
Thereafter, referring to FIG. 1B, a metal layer 12 is formed on top of the substrate 11 by spreading a metal such as Au.
Then, referring to FIG. 1C, the resultant structure is thermally processed at approximately 500° C. As a result, materials in the metal layer 12 are agglomerated, thereby forming catalysts 13. The sizes of the catalysts 13 may be irregular, that is, they have random sizes such as varying thickness and width.
After forming the catalysts 13 as described above, nano wires 14 are formed as the catalysts 13 as nucleation regions, as illustrated in FIG. 1D. The nano wires 14 are formed by supplying, for example, silane (SiH4), which is a compound of silicon and hydrogen, to the catalysts 13 to induce nucleation of Si of silane at the locations where the catalysts 13 are formed. When silane is continually supplied, the nano wires 14 can continuously grow from the bottom of the catalysts 13, as illustrated in FIG. 1D.
As described above, nano wires with desired lengths can be easily formed by appropriately controlling the amount of supplied material gas such as silane. However, the growth of nano wires can be limited by the diameters and distribution, (such as the arrangement, location, formation regions, spacing or density) of the catalysts. Thus it is difficult to accurately control the thickness and distribution of nano wires. In addition, nano wire doping as described above may be performed by mixing a supply gas and a doping material, but nano wires cannot be formed to have a p-n junction structure.